1. Field of the Invention
The present invention relates to techniques for managing shared storage units in a data processing apparatus, for example shared associative tables in multi-core and multi-threaded systems.
2. Description of the Prior Art
It is known for a storage unit such as a cache, translation lookaside buffer (TLB) or branch target buffer (BTB), to be shared by more than one thread being executed by processing circuitry in a data processing apparatus (i.e. the processing circuitry supports more than one hardware thread context). The multiple program threads may comprise separate applications, or may instead comprise different processes within an individual application that are allowed to execute in parallel. One type of processing circuitry that can execute multiple program threads is often referred to as a multi-threaded processor and such multi-threaded processors can take a variety of forms. One example of such a multi-threaded processor is a simultaneous multi-threaded (SMT) processor where the processor can issue operations for multiple different threads at the same time, one particular example being an asymmetric multi-threaded processor. In alternative embodiments, the processing circuitry may comprise multiple separate processor cores (a multi-core system), for example a heterogeneous multi-core system.
In such multi-threaded systems it is further known that some threads have higher priority than others. For example, a thread relating to a task being carried out by the processor or system which is time critical may be designated as high priority, such that when this thread competes with other lower priority threads for the resources of the processor or system, the high priority thread is given precedence.
Asymmetric SMT cores where there is one high priority thread and one lower priority thread in the system are discussed in “Applications of Thread Prioritization in SMT Processors”, S. E. Raasch and S. K. Reinhardt, Proceedings of Multithreaded Execution, Architecture and Compilation Workshop, January 1999, and in “Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance”, G. K. Dorai and D. Yeung, Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques.
There are various situations in such a system where threads may compete for resources, but of particular relevance here is a shared storage unit (also referred to herein as a shared table). Taking the example of a shared cache, the system may be arranged so that, for example, entries made in the cache by lower priority threads can be caused to be evicted by the allocation of entries from high priority threads, but not vice versa. However, whilst this strict preferential treatment for the high priority threads may, in some situations, be appropriate and desirable, in other situations this approach may be too inflexible resulting in poorer overall system performance than might otherwise be achievable.
Hence, it would be desirable to provide an improved technique for managing a shared table, where that table is shared by multiple threads at least one of which has higher priority than the others.